|
[1]
|
Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, and Axel Jantsch.
A reconfigurable design framework for FPGA adaptive computing.
In Proceedings of the International Conference on ReConFigurable
Computing and FPGAs, Cancun, Mexico, December 2009.
[ .pdf ]
|
|
[2]
|
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, and Shuming Chen.
Speedup analysis of data-parallel applications on multi-core NoCs.
In Proceedings of the IEEE International Conference on ASIC
(ASICON), Changsha, China, October 2009.
[ .pdf ]
|
|
[3]
|
Zhonghai Lu and Axel Jantsch.
Trends of terascale computing chips in the next ten years.
In Proceedings of IEEE ASICON 2009, ChangSha, China, October
2009.
[ http ]
|
|
[4]
|
Ming Liu, Wolfganga Kuehn, Zhonghai Lu, and Axel Jantsch.
Run-time partial reconfiguration speed investigation and
architectural design space exploration.
In Proceedings of the International Conference on Field
Programmable Logic and Applications, Prague, Chech Republic, September 2009.
[ .pdf ]
|
|
[5]
|
Ming Liu, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes
Lang, Lu Li, Soeren Lange, Zhen'an Liu, Zhonghai Lu, David Muenchow, Vladimir
Pechenov, Johannes Roskoss, Stephano Spataro, Qiang Wang, and Hao Xu.
Trigger algorithm development on fpga-based compute nodes.
In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.
[ .pdf ]
|
|
[6]
|
Qiang Wang, Axel Jantsch, Dapeng Jin, Andreas Kopp, Wolfgang Kuehn, Johannes
Lang, Soeren Lange, Lu Li, Ming Liu, Zhen'an Liu, Zhonghai Lu, David
Muenchow, Johannes Roskoss, and Hao Xu.
Hardware/software co-design of an ATCA-based computation platform
for data acquisition and triggering.
In 16th IEEE NPSS Real Time Conference, Beijing, May 2009.
[ .pdf ]
|
|
[7]
|
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch,
Roshan Weerasekera, and Hannu Tenhunen.
Scalability of network-on-chip communication architecture for 3-d
meshes.
In Proceedings of the International Symposium on
Networks-on-Chip, San Diego, CA, May 2009.
[ .pdf ]
|
|
[8]
|
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrholzy, Philipp A. Hartmanny,
and Wolfgang Nebel.
High-level estimation and trade-off analysis for adaptive real-time
systems.
In Proceedings of the 16th Reconfigurable Architectures
Workshop, Rome, May 2009.
[ .pdf ]
|
|
[9]
|
Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair Bruce, Pieter van der
Wolf, and Tomas Henriksson.
Flow regulation for on-chip communication.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), April 2009.
[ .pdf ]
|
|
[10]
|
Yuang Zhang, Zhonghai Lu, Axel Jantsch, Li Li, and Minglun Gao.
Towards hierarchical cluster based cache coherence for large-scale
network-on-chip.
In Proceedings of the 4th IEEE International Conference on
Design & Technology of Integrated Systems in Nanoscale Era, Cairo, Egypt,
April 2009.
[ .pdf ]
|
|
[11]
|
Mikael Millberg and Axel Jantsch.
Priority based forced requeue to reduce worst-case latency for bursty
traffic.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), April 2009.
[ .pdf ]
|
|
[12]
|
Jun Zhu, Ingo Sander, and Axel Jantsch.
Buffer minimization of real-time streaming applications scheduling on
hybrid CPU/FPGA architectures.
In Proceedings of the Design and Test Europe Conference (DATE),
April 2009.
[ .pdf ]
|
|
[13]
|
Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, and Li-Rong Zheng.
Analytical evaluation of retransmission schemes in wireless sensor
networks.
In Proceedings of the IEEE 69th Vehicular Technology Conference:
VTC2009-Spring, April 2009.
[ .pdf ]
|
|
[14]
|
Ingo Sander, Alfonso Acosta, and Axel Jantsch.
Hardware design and synthesis in ForSyDe.
In Proceedings of Hardware Design and Functional Languages,
York, UK, March 2009.
[ .pdf ]
|
|
[15]
|
Zhonghai Lu, Dimitris Brachos, and Axel Jantsch.
A flow regulator for on-chip communication.
In Proceedings of the System on Chip Conference, Belfas,
Northern Ireland, 2009.
[ .pdf ]
|
|
[16]
|
Axel Jantsch.
Models of computation for distributed embedded systems.
In Richard Zurawski, editor, Networked Embedded Systems. CRC
Press/Taylor & Francis, 2009.
|
|
[17]
|
Axel Jantsch and Zhonghai Lu.
Resource allocation for quality of service in on-chip communication.
In Fayez Gebali and Haytham Elmiligi, editors, Networks on Chip:
Theory and Practice. Taylor & Francis Group LLC - CRC Press, 2009.
[ .pdf ]
|
|
[1]
|
Jun Zhu, Ingo Sander, and Axel Jantsch.
Energy efficient streaming applications with guaranteed throughput on
MPSoCs.
In Proceedings of the International Conference on Embedded
Software, October 2008.
[ .pdf ]
|
|
[2]
|
Jun Zhu, Ingo Sander, and Axel Jantsch.
Performance analysis of reconfiguration in adaptive real-time
streaming applications.
In Proceedings of the 6th Workshop on Embedded Systems for
Real-Time Multimedia (EstiMedia), Atlanta, USA, October 2008.
[ .pdf ]
|
|
[3]
|
Tiberiu Seceleanu and Axel Jantsch.
Modeling communication with synchronized environments.
Fundamenta Informaticae, 86(3):343-369, October 2008.
[ .pdf ]
|
|
[4]
|
Zhonghai Lu, Axel Jantsch, Erno Salminen, and Cristian Grecu.
Network-on chip micro-benchmarks.
Embedded Systems Design, September 2008.
[ http ]
|
|
[5]
|
Ming Liu, Tiago Perez, Johannes Lang, Shuo Yang, Wolfgang Kuehn, Hao Xu, Dapeng
Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, and Axel Jantsch.
ATCA-based computation platform for data acquisition and triggering
in particle physics experiments.
In Proceedings of the International Conference on Field
Programmable Logic and Applications, September 2008.
[ .pdf ]
|
|
[6]
|
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, and Axel Jantsch.
System-on-an-FPGA design for real-time particle track recognition
and reconstruction in physics experiments.
In Proceedings of the Euromicro Diguital System Design
Conference, September 2008.
[ .pdf ]
|
|
[7]
|
Huimin She, Zhonghai Lu, and Axel Jantsch.
Deterministic worst-case performance analysis for wireless sensor
networks.
In Proceedings of the International Wireless Communications and
Mobile Computing Conference, Crete, Greece, August 2008.
[ .pdf ]
|
|
[8]
|
Zhonghai Lu and Axel Jantsch.
TDM virtual-circuit configuration for network-on-chip.
IEEE Transactions on Very Large Scale Integration Systems,
16(8), August 2008.
[ .pdf ]
|
|
[9]
|
Christoph Grimm, Axel Jantsch, Sandeep Shukla, and Eugenio Villar.
C-based design of embedded systems - editorial.
EURASIP Journal on Embedded Systems, July 2008.
|
|
[10]
|
Deepak Mathaikutty, Hiren Patel, Sandeep Shukla, and Axel Jantsch.
SML-Sys: A functional framework with multiple models of computation
for modeling heterogeneous system.
Design Automation for Embedded Systems, 12(1):1-30, June 2008.
[ http ]
|
|
[11]
|
Zhonghai Lu, Lei Xia, and Axel Jantsch.
Cluster-based simulated annealing for mapping cores onto 2d mesh
networks on chip.
In Proceedings of the IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, April 2008.
[ .pdf ]
|
|
[12]
|
Ingo Sander and Axel Jantsch.
Modelling adaptive systems in ForSyDe.
Electronic Notes in Theoretical Computer Science,
200(2):39-54, February 2008.
[ .pdf ]
|
|
[13]
|
Arseni Vitkovski, Axel Jantsch, Robert Lauter, Raimo Haukilahti, and Erland
Nilsson.
Low-pwer and error protection coding for network-on-chip traffic.
IET Computers and Digital Techniques, 2(6):483-492, 2008.
[ .pdf ]
|
|
[14]
|
Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
Application and verification of local non-semantic-preserving
transformations in system design.
IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems, 27(6):1091-1103, 2008.
[ .pdf ]
|
|
[15]
|
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed
Bechara, Hasan Khalifeh, Axel Jantsch, and Rustam Nabiev.
A multiprocessor system-on-chip for real-time biomedical monitoring
and analysis: ECG prototype architectural design space exploration.
ACM Transactions on Design Automation of Embedded Systems,
13(2), April 2008.
[ .pdf ]
|
|
[1]
|
Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, and Dian Zhou.
Traffic splitting with network calculus for mesh sensor networks.
In International Workshop on Wireless Ad Hoc, Mesh and Sensor
Networks, December 2007.
[ .pdf ]
|
|
[2]
|
Zhonghai Lu and Axel Jantsch.
Slot allocation using logical networks for TDM virtual-circuit
configuration for network-on-chip.
In International Conference on Computer Aided Design (ICCAD),
November 2007.
[ .pdf ]
|
|
[3]
|
Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, and Alistair Bruce.
Network calculus applied to verification of memory access performance
in SoCs.
In Proceedings of the 5th IEEE Workshop on Embedded Systems for
Real-Time Multimedia, October 2007.
[ .pdf ]
|
|
[4]
|
Zhonghai Lu and Axel Jantsch.
Admitting and ejecting flits in wormhole-switched networks on chip.
IET Computers & Digital Techniques, 5(1):546-556, September
2007.
|
|
[5]
|
Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
Synchronization after design refinements with sensitive delay
elements.
In Proceedings of the International Conference on HW/SW Codesign
and System Synthesis, Salzburg, Austria, September 2007.
[ .pdf ]
|
|
[6]
|
Iyad Al-Khatib, Davide Bertozzi, Axel Jantsch, and Luca Benini.
Performance analysis and design space exploration for high-end
biomedical applications: Challenges and solutions.
In Proceedings of the International Conference on Hardware -
Software Codesign and System Synthesis, September 2007.
[ .pdf ]
|
|
[7]
|
Andreas Herrholz, Frank Oppenheimer, P. A. Hartmann, Andreas Schallenberg,
Wolfgang Nebel, Christoph Grimm, Markus Damm, J. Haase, Fernando Herrera,
Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, and Marcos
Martinez.
The ANDRES project: Analysis and design of run-time reconfigurable,
heterogeneous systems.
In Proceedings of the The International Conference on
Field-Programmable Logic, Reconfigurable Computing, and Applications (FPL),
August 2007.
[ .pdf ]
|
|
[8]
|
Mickael Millberg and Axel Jantsch.
Increasing NoC performance and utilisation using a dualpacket exit
strategy.
In 10th Euromicro Conference on Digital System Design, Lubeck,
Germany, August 2007.
[ .pdf ]
|
|
[9]
|
Deepak Mathaikutty, Hiren Patel, Sandeep Shukla, and Axel Jantsch.
EWD: A metamodeling driven customizable multi-moc system modeling
framework.
ACM Transactions on Design Automation of Embedded Systems,
12(3), August 2007.
[ .pdf ]
|
|
[10]
|
Zhonghai Lu, Ming Liu, and Axel Jantsch.
Layered switching for networks on chip.
In Proceedings of the Design Automation Conference, June 2007.
[ .pdf ]
|
|
[11]
|
Andre Ivanov Cristian Grecu and, Partha Pande, Axel Jantsch, Erno Salminen,
Umit Ogras, and Radu Marculescu.
Towards open network-on-chip benchmarks.
In Proceedings of First International Symposium on
Networks-on-Chip, May 2007.
[ .pdf ]
|
|
[12]
|
Zhonghai Lu, Jonas Sicking, Ingo Sander, and Axel Jantsch.
Using synchronizers for refining synchronous communication onto
hardware/software architectures.
In Proceedings of the 18th IEEE/IFIP International Workshop on
Rapid System Prototyping, Porto Alegre, Brasil, May 2007.
[ .pdf ]
|
|
[13]
|
Mickael Millberg and Axel Jantsch.
Improvements of performance and use of buffers in NoCs using dual
packet exit.
In Proceedings of the 1st Symposium on Networks on Chip, May
2007.
poster.
[ .pdf ]
|
|
[14]
|
Per Badlund and Axel Jantsch.
An analytical approach for dimensioning mixed traffic networks.
In Proceedings of the 1st Symposium on Networks on Chip, May
2007.
poster.
[ .pdf ]
|
|
[15]
|
Andreas Herrholz, Frank Oppenheimer, Andreas Schallenberg, Wolfgang Nebel,
Christoph Grimm, Markus Damm, Fernando Herrera, Eugenio Villar, Ingo Sander,
Axel Jantsch, Anne-Marie Fouilliart, and Marcos Martinez.
ANDRES - analysis and design of run-time reconfigurable,
heterogeneous systems.
In Workshop on Reconfigurable Systems at DATE, April 2007.
[ .pdf ]
|
|
[16]
|
Ingo Sander and Axel Jantsch.
Modelling adaptive systems in ForSyDe.
In Proceedings of the First Workshop on Verification of Adaptive
Systems (VerAS), pages 39-54, Kaiserslauten, 2007.
[ .pdf ]
|
|
[17]
|
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez,
and Zhenan Liu.
Hardware/software co-design of a general-purpose computation platform
in particle physics.
In Proceedings of the ICFPT, 2007.
[ .pdf ]
|
|
[18]
|
Huimin She, Zhonghai Lu, Axel Jantsch, and Dian Zhou.
A network-based system architecture for remote medical applications.
In Proceedings of the Asia-Pacific Advanced Network Meeting,
2007.
[ .pdf ]
|
|
[19]
|
Tarvo Raudvere, Ingo Sander, and Axel Jantsch.
A synchronization algorithm for local temporal refinements in
perfectly synchronous models with nested feedback loops.
In Proceedings of the Great Lake Symposium on VLSI (GLSVLSI),
2007.
[ .pdf ]
|
|
[20]
|
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch,
Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, and Sven
Jonsson.
Hardware/software architecture for real-time ECG monitoring and
analysis leveraging MPSoC technology.
Transactions on High-Performance Embedded Architectures and
Compilers (HiPEAC), I(1):239-258, 2007.
LNCS 4050.
[ .pdf ]
|
|
[1]
|
Jun Zhu, Axel Jantsch, and Ingo Sander.
SDF to synchronous cross domain analysis in ForSyDe stream
processing framework.
In 2nd HiPEAC Industrial Workshop, October 2006.
[ .pdf ]
|
|
[2]
|
T. Seceleanu, A. Jantsch, and H. Tenhunen.
On-chip distributed architectures.
In Proceedings of the IEEE International SOC Conference, pages
329 - 330, September 2006.
|
|
[3]
|
Rikard Thid, Ingo Sander, and Axel Jantsch.
Flexible bus and NoC performance analysis with configurable
synthetic workloads.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ .pdf ]
|
|
[4]
|
Sandro Penolazzi and Axel Jantsch.
A high level power model for the Nostrum NoC.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ .pdf ]
|
|
[5]
|
Liang Guang and Axel Jantsch.
Adaptive power management for the on-chip communication network.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ .pdf ]
|
|
[6]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Towards performance-oriented pattern-based refinement of synchronous
models onto NoC communication.
In 9th Euromicro Conference on Digital System Design (DSD
2006), August 2006.
[ .pdf ]
|
|
[7]
|
Iyad Al-Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed
Bechara, Hasan Khalifeh, Axel Jantsch, and Rustam Nabiev.
A multiprocessor system-on-chip for real-time biomedical monitoring
and analysis: Architectural design space exploration.
In Proceedings of the Design Automation Conference, July 2006.
[ .pdf ]
|
|
[8]
|
Weixing Wang and Axel Jantsch.
A new protocol for electing cluster head based on maximum residual
energy.
In Proceedings of the IEEE International Cross-Layer Designs and
Protocols Symposium, July 2006.
|
|
[9]
|
Tiberiu Seceleanu and Axel Jantsch.
Communicating with synchronized environments.
In Proceedings of the Sixth International Conference on
Application of Concurrency to System Design, June 2006.
[ .pdf ]
|
|
[10]
|
Axel Jantsch.
Models of computation for networks on chip.
In Proceedings of the Sixth International Conference on
Application of Concurrency to System Design, June 2006.
invited paper.
[ .pdf ]
|
|
[11]
|
Zhonghai Lu, Bei Yin, and Axel Jantsch.
Connection-oriented multicasting in wormhole-switched networks on
chip.
In Proceedings of the IEEE Computer Society Annual Symposium on
VLSI, March 2006.
[ .pdf ]
|
|
[12]
|
Axel Jantsch.
Nocsim: A NoC Simulator.
School of Information and Communication Technology, Royal Institute
of Technology, Stockholm, version 0.4 alpha edition, 2006.
|
|
[13]
|
Zhonghai Lu, Mingchen Zhong, and Axel Jantsch.
Evaluation of onchip networks using deflection routing.
In Proceedings of GLSVLSI, 2006.
[ .pdf ]
|
|
[14]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Refining synchronous communication onto network-on-chip best-effort
services.
In Alain Vachoux, editor, Advances in Design and Specification
Languages for SoCs - Selected Contributions from FDL 2005. Springer
Verlag, 2006.
[ .pdf ]
|
|
[15]
|
Deepak Abraham Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch.
UMoC++: A C++-based multi-MoC modeling environment.
In Alain Vachoux, editor, Advances in Design and Specification
Languages for SoCs - Selected Contributions from FDL'05, chapter 7. Springer
Verlag, 2006.
[ .pdf ]
|
|
[16]
|
Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch,
Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, and Sven
Jonsson.
MPSoC ECG biochip: A multiprocessor System-on-Chip for
real-time human heart monitoring and analysis.
In Proceedings of the ACM Computing Frontiers, 2006.
[ .pdf ]
|
|
[1]
|
Weixing Wang, Axel Jantsch, and Shuran Song.
An algorithm of electing cluster head in beacon node distributions
based on maximum residual energy.
In Proceedings of Annual Conference on Chinese Society of
Agricultural Engineering, volume 3:535-539, Guangzhou City, P. R. of China,
December 2005.
[ http ]
|
|
[2]
|
Tarvo Raudvere, Ashish K. Singh, Ingo Sander, and Axel Jantsch.
System level verification of digital signal processing applications
based on the polynomial abstraction technique.
In Proceedings of the Internatipnal Conference on Computer Aided
Design (ICCAD), November 2005.
|
|
[3]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
Refinement of a perfectly synchronous communication model onto
Nostrum NoC best-effort communication.
In Proceedings of the Forum on Design Languages, September
2005.
[ .pdf ]
|
|
[4]
|
Deepak Abraham Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch.
UMoC++: Modeling environment for heterogeneous systems based on
generic MoCs.
In Proceedings of the Forum on Design Languages, September
2005.
|
|
[5]
|
Zhonghai Lu, Li Tong, Bei Yin, and Axel Jantsch.
A power efficient flit-admission scheme for wormhole-switched
networks on chip.
In Proceedings of the 9th World Multi-Conference on Systemics,
Cybernetics and Informatics, July 2005.
[ .pdf ]
|
|
[6]
|
Zhonghai Lu and Axel Jantsch.
Traffic configuration for evaluating networks on chips.
In Proceedings of the 5th International Workshop on Systems on
Chip (IWSOC), July 2005.
[ .pdf ]
|
|
[7]
|
Iyad Al Khatib, Axel Jantsch, Bassam Kayal, Rustam Nabiev, and Sven Jonsson.
Wireless network-on-chips as autonomous systems: A novel solution for
biomedical healthcare and space exploration sensor-networks.
In Proceedings of the Infocom 2005 Conference - Student
Workshop, March 2005.
[ .pdf ]
|
|
[8]
|
Iyad Al Khatib, Axel Jantsch, and Mohammad Saleh.
Simulation of real home healthcare sensor networks utilizing ieee
802.11g biomedical network-on-chip.
In Proceedings of REALWAN, Stockholm, 2005.
|
|
[9]
|
Axel Jantsch, Robert Lauter, and Arseni Vitkowski.
Power analysis of link level and end-to-end data protection on
networks on chip.
In Proceedings of the IEEE International Symposium on Circuits
and Systems, 2005.
[ .pdf ]
|
|
[10]
|
Zhonghai Lu, Axel Jantsch, and Ingo Sander.
Feasibility analysis of messages for on-chip networks using wormhole
routing.
In Proceedings of the Asian Pacific Design Automation
Conference, 2005.
[ .pdf ]
|
|
[11]
|
Axel Jantsch and Ingo Sander.
Models of computation and languages for embedded system design.
IEE Proceedings on Computers and Digital Techniques,
152(2):114-129, March 2005.
Special issue on Embedded Microelectronic Systems; Invited paper.
[ .pdf ]
|
|
[12]
|
Axel Jantsch and Ingo Sander.
Models of computation in the design process.
In Bashir M Al-Hashimi, editor, SoC: Next Generation
Electronics. IEE, 2005.
Invited contribution.
[ .pdf ]
|
|
[13]
|
Axel Jantsch.
Models of embedded computation.
In Richard Zurawski, editor, Embedded Systems Handbook. CRC
Press, 2005.
Invited contribution.
[ .pdf ]
|
|
[1]
|
Arseni Vitkovski, Raimo Haukilahti, Axel Jantsch, and Erland Nilsson.
Low-power and error coding for network-on-chip traffic.
In Proceedings of the IEEE NorChip Conference, November 2004.
[ .pdf ]
|
|
[2]
|
Zhonghai Lu and Axel Jantsch.
Flit ejection in on-chip wormhole-switched networks with virtual
channels.
In Proceedings of the IEEE NorChip Conference, November 2004.
[ .pdf ]
|
|
[3]
|
Zhonghai Lu and Axel Jantsch.
Flit admission in on-chip wormhole-switched networks with virtual
channels.
In Proceedings of the International Symposium on System-on-Chip
2003, November 2004.
[ .pdf ]
|
|
[4]
|
Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch,
and Hannu Tenhunen.
A study on the implementation of 2-D mesh based networks on chip in
the nanoregime.
Integration - The VLSI Journal, 38(1):3-17, October 2004.
|
|
[5]
|
Abhijit K. Deb, Axel Jantsch, and Johnny Öberg.
System design for dsp applications in transaction level modeling
paradigm.
In Proc. Design Automation Conf. (DAC), pages 466-471, San
Diego, California, June 2004.
[ .pdf ]
|
|
[6]
|
Heiko Zimmer and Axel Jantsch.
Error-tolerant interconnect schemes.
In Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch,
editors, Interconnect-Centric Design for Advanced SoCs and NoCs,
chapter 6. Kluwer Academic Publisher, April 2004.
[ .pdf ]
|
|
[7]
|
Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch, editors.
Interconnect-Centri Design for Advanced SoCs and NoCs.
Kluwer Academic Publisher, April 2004.
|
|
[8]
|
Ingo Sander, Axel Jantsch, and Hannu Tenhunen.
The platform as interface in a SoC design curriculum.
In Proceedings of te 5t European Worksop on Microelectronics
Education, April 2004.
|
|
[9]
|
Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch.
Guaranteed bandwidth using looped containers in temporally disjoint
networks within the Nostrum network on chip.
In Proceedings of the Design Automation and Test in Europe
Conference, Paris, France, February 2004.
|
|
[10]
|
Axel Jantsch, Johnny Öberg, and Hannu Tenhunen, editors.
Journal of Systems Architecture, volume 50.
Elseviere, February 2004.
Special Issue on Networks on Chip.
|
|
[11]
|
Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, and Axel Jantsch.
Polynomial abstraction for verification of sequentially implemented
combinational circuits.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), February 2004.
interactive presentation.
|
|
[12]
|
Mikael Millberg, Erland Nilsson, Rikard Thid, and Axel Jantsch.
Guaranteed bandwidth using looped containers in temporally disjoint
networks within the Nostrum network on chip.
In Proceedings of the Design Automation and Test Europe
Conference (DATE), February 2004.
[ .pdf ]
|
|
[13]
|
Abhijit K. Deb, Axel Jantsch, and Johnny Öberg.
System design for dsp applications using the MASIC methodology.
In Proceedings of the Design Automation and Test Europe (DATE),
February 2004.
|
|
[14]
|
Martti Forsell, Juha-Pekka Soininen, Kari Tiensyriä, Axel Jantsch, Klaus
Kronlöf, and Bojidar Hadjiski.
Networks on chip: Approaches and challenges.
In Research and Development Activities in Telecommunication
Systems. VTT Electronics, 2004.
[ http ]
|
|
[15]
|
Axel Jantsch, Johnny Öberg, and Hannu Tenhunen.
Special issue on networks on chip - guest editor's introduction.
Journal of Systems Architecture, 50(2-3), Februry 2004.
[ .pdf ]
|
|
[16]
|
Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, and Axel Jantsch.
The Nostrum backbone - a communication protocol stack for networks
on chip.
In Proceedings of the VLSI Design Conference, Mumbai, India,
January 2004.
[ .pdf ]
|
|
[17]
|
Ingo Sander and Axel Jantsch.
System modeling and transformational design refinement in ForSyDe.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 23(1):17-32, January 2004.
[ .pdf ]
|
|
[1]
|
D. Pamunuwa, J. Öberg, L. R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen.
Layout, performance and power trade-offs in mesh-based
network-on-chip architectures.
In IFIP International Conference on Very Large Scale Integration
(VLSI-SOC), Darmstadt, Germany, December 2003.
[ .pdf ]
|
|
[2]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A group of subword instructions and design issues for network
processing RISC cores.
In Proceedings of the IEEE NorChip Conference, November 2003.
|
|
[3]
|
Richard Thid, Mikael Millberg, and Axel Jantsch.
Evaluating NoC communication backbones with simulation.
In Proceedings of the IEEE NorChip Conference, November 2003.
[ .pdf ]
|
|
[4]
|
Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, and Axel Jantsch.
Verification of design decisions in forsyde.
In Proceedings of the CODES-ISSS Conference, October 2003.
|
|
[5]
|
Heiko Zimmer and Axel Jantsch.
A fault model notation and error-control scheme for switch-to-switch
buses in a network-on-chip.
In Proceedings of the CODES-ISSS Conference, October 2003.
[ .pdf ]
|
|
[6]
|
Ingo Sander, Axel Jantsch, and Zhonghai Lu.
Development and application of design transformations in ForSyDe.
IEE Proceedings on Computers and Digital Technique,
150(5):313-320, September 2003.
|
|
[7]
|
Axel Jantsch.
NoCs: A new contract between hardware and software.
In Proceedings of the Euromicro Symposium on Digital System
Design, September 2003.
Invited keynote.
[ .pdf ]
|
|
[8]
|
Axel Jantsch.
Modeling Embedded Systems and SoCs - Concurrency and Time in
Models of Computation.
Systems on Silicon. Morgan Kaufmann Publishers, June 2003.
[ http ]
|
|
[9]
|
Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Simulation and analysis of embedded DSP systems using Petri nets.
In Proceedings of the 14th IEEE International Workshop on Rapid
System Prototyping, June 2003.
|
|
[10]
|
Erland Nilsson, Mikael Millberg, Johnny Öberg, and Axel Jantsch.
Load distribution with the proximity congestion awareness in a
network on chip.
In Proceedings of the Design Automation and Test Europe (DATE),
pages 1126-1127, March 2003.
[ .pdf ]
|
|
[11]
|
Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Simulation and analysis of embedded DSP systems using MASIC
methodology.
In Proceedings of the Design Automation and Test Europe (DATE),
March 2003.
|
|
[12]
|
Ingo Sander, Axel Jantsch, and Zhonghai Lu.
The development and application of formal design transformations in
ForSyDe.
In Proceedings of the Design Automation and Test Europe (DATE),
March 2003.
[ .pdf ]
|
|
[13]
|
Axel Jantsch and Hannu Tenhunen, editors.
Networks on Chip.
Kluwer Academic Publishers, February 2003.
[ http ]
|
|
[14]
|
Axel Jantsch and Hannu Tenhunen.
Will networks on chip close the productivity gap?
In Axel Jantsch and Hannu Tenhunen, editors, Networks on Chip,
chapter 1, pages 3-18. Kluwer Academic Publishers, February 2003.
[ .pdf ]
|
|
[15]
|
Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku,
and Shashi Kumar.
Extending platform-based design to network on chip systems.
In Proceedings of the International Conference on VLSI Design,
January 2003.
[ .pdf ]
|
|
[1]
|
Yi-Ran Sun, Shashi Kumar, and Axel Jantsch.
Simulation and evaluation of a network on chip architecture using
ns-2.
In Proceedings of the IEEE NorChip Conference, November 2002.
|
|
[2]
|
Zhonghai Lu, Ingo Sander, and Axel Jantsch.
A case study of hardware and software synthesis in ForSyDe.
In Proceedings of the 15th International Symposium on System
Synthesis, Kyoto, Japan, October 2002.
|
|
[3]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
Two special register addressing modes for internet protocol
processing.
In Proc. of International Network Conference, Plymouth, United
kingdom, July 2002.
|
|
[4]
|
Axel Jantsch.
Network on chip.
In Proceedings of the Conference Radio vetenskap och
Kommunication, Stockholm, June 2002.
[ .pdf ]
|
|
[5]
|
Ingo Sander and Axel Jantsch.
Transformation based communication and clock domain refinement for
system design.
In Proceedings of Design Automation Conference, June 2002.
[ .pdf ]
|
|
[6]
|
Per Bjureus, Mickael Millberg, and Axel Jantsch.
FPGA resource and timing estimation from Matlab execution traces.
In Proceedings of the International Workshop on
Hardware/Software Codesign, May 2002.
|
|
[7]
|
Tero Nurmi, Hannu Tenhunen, Li-Rong Zheng, Axel Jantsch, Jari Nurmi, and Jouni
Isoaho.
Physical performance modelling for platform-based SoC design.
In Proceedings of the 4th European Workshop on Microelectronics
Education, May 2002.
|
|
[8]
|
Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael
Millberg, Johnny Öberg, Kari Tiensyrjä, and Ahmed Hemani.
A network on chip architecture and design methodology.
In Proceedings of IEEE Computer Society Annual Symposium on
VLSI, April 2002.
[ .pdf ]
|
|
[9]
|
Abhijit Kumar Deb, Johnny Oberg, and Axel Jantsch.
Performance analsysi and architectural refinement of embedded DSP
systems in the MASIC methodology.
In Proceedings of Swedish System-on-Chip Conference, March
2002.
|
|
[10]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
Load/store unit design of a programmable internet protocol processor.
In Proceedings of Swedish System-on-Chip Conference, March
2002.
|
|
[11]
|
Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Dilian Gurov, and Axel
Jantsch.
The forsyde semantics.
In Proceedings of Swedish System-on-Chip Conference, March
2002.
|
|
[1]
|
Per Bjuréus and Axel Jantsch.
Performance analysis with confidence intervals for embedded software
processes.
In Proceedings of the International Symposium on System
Synthesis (ISSS), October 2001.
[ .pdf ]
|
|
[2]
|
Abhijit K. Deb, Johnny Öberg, and Axel Jantsch.
Control and communication performance analysis of embedded DSP
systems in the MASIC methodology.
In Proceedings of the International Symposium on System
Synthesis (ISSS), October 2001.
[ .pdf ]
|
|
[3]
|
Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Li-Rong Zheng, Shashi Kumar,
Mikael Millberg, and Johnny Öberg.
Networks on chip.
In Workshop at the European Solid State Circuits Conference,
September 2001.
|
|
[4]
|
Axel Jantsch, Ingo Sander, and Wenbiao Wu.
The usage of stochastic processes in embedded system specifications.
In Proceedings of the Ninth International Symposium on
Hardware/Software Codesign, April 2001.
[ .pdf ]
|
|
[5]
|
Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, and Ahmed Hemani.
Grammar-based design.
Journal of Systems Architecture, 47(3-4):225-240, April 2001.
|
|
[6]
|
Per Bjuréus and Axel Jantsch.
Heterogenous system-level cosimulation with SDL and Matlab.
In Jean Mermet, editor, Electronic Chips & System Design
Languages, chapter 12, pages 145-157. Kluwer Academic Publisher, 2001.
[ .pdf ]
|
|
[7]
|
Per Bjuréus and Axel Jantsch.
Modeling of mixed control and dataflow systems in MASCOT.
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 9(5):690-704, October 2001.
|
|
[8]
|
A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, A. Hemani, Peeter
Ellervee, and Mattias O'Nils.
A comparison of six languages for system level description of telecom
applications.
In Jean Mermet, editor, Electronic Chips & System Design
Languages, chapter 15, pages 181-192. Kluwer Academic Publisher, 2001.
[ .pdf ]
|
|
[9]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A flexible register access control for programmable protocol
processors.
In Proceedings of the 44th Midwest Symposium on Circuits and
Systems (MWSCAS), August 2001.
[ .pdf ]
|
|
[10]
|
Mattias O'Nils and Axel Jantsch.
Device driver and DMA controller synthesis from HW/SW
communication protocol specifications.
Design Automation of Embedded Systems, 6(2):177 - 207, April
2001.
[ .pdf ]
|
|
[1]
|
Per Bjuréus and Axel Jantsch.
MASCOT: A specification and cosimulation method integrating data
and control flow.
In Proceedings of the Design and Test Europe Conference (DATE),
2000.
[ .pdf ]
|
|
[2]
|
Johan Ditmar, Kjell Torkelsson, and Axel Jantsch.
A dynamically reconfigurable fpga-based content addressable memory
for internet protocol characterization.
In Reiner W. Hartenstein and Herbert Grunbacher, editors,
Proceedings of the 10th International Conference on Field Programmable Logic
and Applications, volume 1896 of Lecture Notes in Computer Science,
pages 19-28. Springer Verlag, August 2000.
|
|
[3]
|
Ahmed Hemani, Axel Jantsch, Shashi Kumar, Adam Postula, Johnny Öberg, Mikael
Millberg, and Dan Lindqvist.
Network on chip: An architecture for billion transistor era.
In Proceeding of the IEEE NorChip Conference, November 2000.
[ .pdf ]
|
|
[4]
|
Axel Jantsch, Johann Notbauer, and Thomas Albrecht.
Functional validation for large telecom systems.
Design Automation of Embedded Systems, Kluwer, 5(1), February
2000.
[ .pdf ]
|
|
[5]
|
Axel Jantsch and Per Bjuréus.
Composite signal flow: A computational model combining events,
sampled streams, and vectors.
In Proceedings of the Design and Test Europe Conference (DATE),
2000.
[ .pdf ]
|
|
[6]
|
Axel Jantsch and Ingo Sander.
On the roles of functions and objects in system specification.
In Proceedings of the International Workshop on
Hardware/Software Codesign, 2000.
[ .pdf ]
|
|
[7]
|
Axel Jantsch, Shashi Kumar, and Ahmed Hemani.
A metamodel for studying concepts in electronic system design.
IEEE Design & Test of Computers, 17(3):78-85, July-September
2000.
[ .pdf ]
|
|
[8]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A simple transition control for fsm programmable protocol processors.
In Proceedings of the 43rd Midwest Symposium on Circuits and
Systems (MWSCAS), August 2000.
[ .pdf ]
|
|
[9]
|
Yutai Ma, Axel Jantsch, and Hannu Tenhunen.
A programmable protocol processor architecture for high speed
internet protocol processing.
In Proceedings of the IEEE NORCHIP Conference, November 2000.
[ http ]
|
|
[10]
|
Patrick Schaumont, Mary Sheeran, Satnam Singh, and Axel Jantsch.
Object oriented approach versus functional approach in system design.
In Proceedings of the Forum on Design Languages, 2000.
|
|
[11]
|
Wenbiao Wu, Ingo Sander, and Axel Jantsch.
Transformational system design based on a formal computational model
and skeletons.
In Proceedings of the Forum on Design Languages, September
2000.
[ .pdf ]
|
|
[1]
|
Per Bjuréus and Axel Jantsch.
Heterogenous system-level cosimulation with SDL and Matlab.
In Proceedings of the Forum on Design Languages (FDL), 1999.
|
|
[2]
|
Wolfgang Horn, Bengt Svantesson, Shashi Kumar, Axel Jantsch, and Ahmed Hemani.
Hardware synthesis of an atm multiplexer modelled in SDL: A case
study.
In Proceedings of the IEEE Computer Society Annual Workshop on
VLSI, 1999.
|
|
[3]
|
Axel Jantsch, Shashi Kumar, and Ahmed Hemani.
The Rugby model: A framework for the study of modelling, analysis,
and synthesis concepts in electronic systems.
In Proceedings of Design Automation and Test in Europe (DATE),
1999.
|
|
[4]
|
Axel Jantsch.
Formal system specification models for verification and refinement.
In EDA-Traff'99, 1999.
|
|
[5]
|
Axel Jantsch.
Integrated electronic systems program - a national research program.
In EDA-Traff'99, 1999.
|
|
[6]
|
Thomas Meincke, Axel Jantsch, Peeter Ellervee, Ahmed Hemani, and Hannu
Tenhunen.
A generic scheme for communication representation and mapping.
In Proceedings of to IEEE Norchip Conference, 1999.
|
|
[7]
|
Henrik Olson, Axel Jantsch, and Hannu Tenhunen.
Floating- to fixed-point refinement in Matlab with an
object-oriented library.
In Proceedings of the IEEE Norchip Conference, 1999.
|
|
[8]
|
Mattias O'Nils and Axel Jantsch.
Synthesis of DMA controllers from architecture independent
descriptions of HW/SW communication protocols.
In Proceedings of the Twelfth International Conference on VLSI
Design, January 1999.
|
|
[9]
|
Mattias O'Nils and Axel Jantsch.
Operating system sensitive device driver synthesis from
implementation independent protocol specification.
In Proceedings of Design Automation and Test in Europe, 1999.
|
|
[10]
|
Ingo Sander and Axel Jantsch.
System synthesis utilizing a layered functional model.
In Proceedings of the 7th International Workshop on
Hardware/Software Codesign, pages 136-141, May 1999.
|
|
[11]
|
Ingo Sander and Axel Jantsch.
Formal design based on the synchronous approach, functional models
and skeletons.
In Proceedings of the Twelfth International Conference on VLSI
Design, 1999.
|
|
[12]
|
Ingo Sander and Axel Jantsch.
System synthesis based on a formal computational model and skeletons.
In Proceedings of the IEEE Computer Society Annual Workshop on
VLSI, 1999.
|
|
[1]
|
Peeter Ellervee, Shashi Kumar, Axel Jantsch, Bengt Svantesson, Thomas Meincke,
and Ahmed Hemani.
IRSYD: An internal representation for heterogeneous embedded
systems.
In Proceedings of the 16th NORCHIP Conference, 1998.
|
|
[2]
|
A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, and A. Hemani.
Comparison of six languages for system level descriptions of telecom
systems.
In Proceedings of the Forum on Design Languages, volume 2,
1998.
[ .pdf ]
|
|
[3]
|
Axel Jantsch, Johnny Öberg, and Ahmed Hemani.
Is there a niche for a general protocol processor ?
In Proceeedings of 16th NORCHIP Conference, 1998.
|
|
[4]
|
Johnny Öberg, Anshul Kumar, and Axel Jantsch.
An object-oriented concept for intelligent library functions.
In Proceedings of the Eleventh International Conference on VLSI
Design, January 1998.
|
|
[5]
|
Johnny Oeberg, Axel Jantsch, and Ahmed Hemani.
Validation of interface protocols using grammar-based models.
In Proceedings of the IEEE International High Level Design
Validation and Test Workshop, 1998.
|
|
[6]
|
Mattias O'Nils, Johnny Öberg, and Axel Jantsch.
Grammar based modelling and synthesis of device drivers and bus
interfaces.
In Proceedings of the 24th Euromicro Conference, short
contribution, Vasteras, 1998.
|
|
[7]
|
Mattias O'Nils and Axel Jantsch.
Multi-phase validation of hardware/software interfaces based on
generated simulation models.
In Proceedings of the IEEE International High Level Design
Validation and Test Workshop, November 1998.
|
|
[8]
|
Mattias O'Nils and Axel Jantsch.
Refinement of HW/SW communication channels: Case study and
comparison.
In Proceedings of the 16th NORCHIP Conference, November 1998.
|
|
[9]
|
Mattias O'Nils and Axel Jantsch.
HW/SW interface validation in ip based system design.
In Proceedings of the International Workshop on IP Based
Synthesis and System Design, December 1998.
|
|
[1]
|
Shashi Kumar, Axel Jantsch, Peeter Ellervee, Ahmed Hemani, and Anshul Kumar.
Internal representation for specification and design of heterogenous
systems.
In Third Workshop on Systems Design Languages, Italy, July
1997.
|
|
[2]
|
L. Hellberg, A. Hemani, J. Isoaho, A. Jantsch, M. Mokhtari, and H. Tenhunen.
System oriented vlsi curriculum at kth.
In Proceedings of the International Conference on
Microelectronic Systems Educations, MSE97, 1997.
|
|
[3]
|
L. Hellberg, A. Hemani, J. Isoaho, A. Jantsch, M. Mokhtari, and H. Tenhunen.
Integration of physical and functional electronic system
representations in electronic curriculum.
In Proceedings of the 15th NORCHIP Conference, 1997.
|
|
[4]
|
Axel Jantsch.
Limitations of interactive design.
In Workshop on Electronic Design Processes, 1997.
http://www.cse.nd.edu/ cseda/edpw97/.
|
|
[5]
|
Axel Jantsch, Johann Notbauer, and Thomas Albrecht.
Testcase development for large telecom systems.
In Proceedings of the International High-level Design Validation
and test Workshop, November 1997.
[ .pdf ]
|
|
[6]
|
Mattias O'Nils and Axel Jantsch.
Communication in hardware/software embedded systems - a taxonomy and
problem formulation.
In Proceedings of the 15th NORCHIP Conference, November 1997.
|
|
[1]
|
Mattias O'Nils, Axel Jantsch, Ahmed Hemani, and Hannu Tenhunen.
Interactive hardware-software partitioning and memory allocation
based on data transfer profiling.
In International Conference on Recent Advances in Mechatronics,
August 1995.
[ .pdf ]
|
|
[2]
|
T. Lazraq, B. Svantesson, A. Jantsch, and A. Hemani.
Modelling of operation and maintance functions in the atm network.
In Proc. of the 9th European Simulation Multiconference, June
1995.
|
|
[3]
|
Ahmed Hemani, Bengt Svantesson, Peeter Ellervee, Adam Postula, Axel Jantsch,
and Hannu Tenhunen.
Trade-offs in high-level synthesis of telecommunication circuits.
In Proceedings of SASIMI'95, Japan, 1995.
|
|
[4]
|
A. Hemani, B. Svantesson, P. Ellervee, A.Postula, J. Öberg, A.Jantsch, and
H. Tenhunen.
High-level synthesis of control and memory intensive communication
systems.
In Proceedings of the 1995 ASIC Conference and Exhibit, Austin,
Texas, September 1995.
|
|
[5]
|
Johnny Öberg, Peeter Ellervee, Mehran Mokhtari, Axel Jantsch, and Ahmed Hemani.
A 1 gips peak performance multi-threaded processor core using
interleaved processing and a revolving register file targeted for gaas.
In 5th Swedish Workshop on Computer System Architecture
(DSA'95), 1995.
|
|
[1]
|
Peeter Ellervee, Johnny Öberg, Axel Jantsch, and Ahmed Hemani.
Neural network based estimator to explore the design space at system
level.
In Procceedings of the Biennial Baltic Electronic Conference,
Tallin, October 1994.
|
|
[2]
|
Jouni Isoaho and Axel Jantsch.
DSP development with full-speed prototyping based on HW-SW
codesign techniques.
In Proc. of the Fourth International Workshop on Field
programmable Logic and Applications, Prague, FPL'94, September 1994.
|
|
[3]
|
Axel Jantsch and Jouni Isoaho.
A versatile design validation environment by means of software
execution, hardware simulation, and emulation.
In Proc. of the 36th SIMS Simulation Conference, pages 322 -
325. Scandinavian Simulation Society, August 1994.
|
|
[4]
|
Peeter Ellervee, Axel Jantsch, Johnny Öberg, Ahmed Hemani, and Hannu Tenhunen.
Exploring asic design space at system level with a neural network
estimator.
In 7th Annual IEEE International ASIC Conference, ASIC'94,
1994.
|
|
[5]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, Ahmed Hemani, and Hannu Tenhunen.
A software oriented approach to hardware/software codesign.
In Proceedings of the Poster Session of CC'94, International
Conference on Compiler Construction, Edinburgh, April 1994.
|
|
[6]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, and Ahmed Hemani.
A case study on hardware/software partitioning.
In Proceedings of IEEE Workshop on FPGAs for Custom Computing
Machines, Napa, CA, April 1994.
|
|
[7]
|
Axel Jantsch, Peeter Ellervee, Johnny Öberg, Ahmed Hemani, and Hannu Tenhunen.
Hardware-software partitioning and minimizing memory interface
traffic.
In Proceedings of EURO-DAC '94, Grenoble, France, September
1994.
[ .pdf ]
|
|
[8]
|
Axel Jantsch, Jouni Isoaho, and Johnny Öberg.
Hardware-software codesign for multirate DSP system development.
In Poster session of Third International Workshop on
Hardware-Software Codesign, Grenoble, September 1994.
|
|
[9]
|
J. Öberg, P. Ellervee, M. Mokhtari, and A. Jantsch.
Design of a 1 gips peak performance processor using gaas technology.
In Proceedings of the IEEE NORCHIP Conference, November 1994.
|
|
[10]
|
J. Öberg, J. Isoaho, P. Ellervee, A. Jantsch, and A. Hemani.
Babbage - a rule based tool for synthesis of hardware systems.
In Proceedings of the IEEE NORCHIP Conference, November 1994.
|